The present disclosure relates generally to semiconductor devices, and more specifically, to improving gate height control of gate stacks in a finFET semiconductor device.
A replacement metal gate (RMG) process may be employed in a semiconductor fabrication processes to form a metal gate stack in a semiconductor device. The conventional RMG process typically employs a hardmask comprising, for example nitride, which is formed on an upper surface of a dummy gate. The dummy gate is ultimately removed and replaced with a metal gate. Prior to incorporating the metal gate, however, the hardmask serves to protect the dummy gate from epitaxial growth and erosion during the spacer etching process for example.
In semiconductor devices including both an N-region and a P-region in close proximity of one another, an N—P overlap region may exist where the n-region and the p-region overlap with each other. The N—P overlap region may be unresponsive to the etching process used to remove the hardmask, thereby causing a variation in the height of the hardmask layer. Consequently, the hardmask layer may require over-etching to completely remove the hardmask from the dummy gate. However, the over-etching may cause spacers divots, i.e., excess erosion of the spacers surrounding the gate stack, which leads to poor gate height control. Further, the spacer divots may lead to the formation of a metal gate stack that extends laterally beyond the width of the spacers allowing for adjacent metal gate stacks to contact one another.